Towards a Design Flow for Reversible Logic

2010

Wille, Robert , Drechsler, Rolf 저자(글)

Springer · 2010년 08월 18일

책 소개

작가정보

저자(글) Wille, Robert

저자(글) Drechsler, Rolf

목차

• Introduction	p. 1
  Preliminaries	p. 7
  Background	p. 7
  Reversible Functions	p. 7
  Reversible Circuits	p. 9
  Quantum Circuits	p. 13
  Decision Diagrams	p. 16
  Binary Decision Diagrams	p. 17
  Quantum Multiple-valued Decision Diagrams	p. 19
  Satisfiability Solvers	p. 21
  Boolean Satisfiability	p. 21
  Extended SAT Solvers	p. 22
  Synthesis of Reversible Logic	p. 27
  Current Synthesis Steps	p. 28
  Embedding Irreversible Functions	p. 28
  Transformation-based Synthesis	p. 30
  BDD-based Synthesis	p. 31
  General Idea	p. 32
  Exploiting BDD Optimization	p. 34
  Theoretical Consideration	p. 37
  Experimental Results	p. 39
  SyReC: A Reversible Hardware Language	p. 46
  The SyReC Language	p. 47
  Synthesis of the Circuits	p. 50
  Experimental Results	p. 53
  Summary and Future Work	p. 56
  Exact Synthesis of Reversible Logic	p. 57
  Main Flow	p. 58
  SAT-based Exact Synthesis	p. 61
  Encoding for Toffoli Circuits	p. 61
  Encoding for Quantum Circuits	p. 65
  Handling Irreversible Functions	p. 68
  Experimental Results	p. 70
  Improved Exact Synthesis	p. 76
  Exploiting Higher Levels of Abstractions	p. 77
  Quantified Exact Synthesis	p. 81
  Experimental Results	p. 84
  Summary and Future Work	p. 91
  Embedding of Irreversible Functions	p. 93
  The Embedding Problem	p. 94
  Don't Care Assignment	p. 96
  Methods	p. 96
  Experimental Results	p. 99
  Synthesis with Output Permutation	p. 100
  General Idea	p. 102
  Exact Approach	p. 104
  Heuristic Approach	p. 105
  Experimental Results	p. 106
  Summary and Future Work	p. 111
  Optimization	p. 113
  Adding Lines to Reduce Circuit Cost	p. 114
  General Idea	p. 114
  Algorithm	p. 116
  Experimental Results	p. 117
  Reducing the Number of Circuit Lines	p. 124
  General Idea	p. 125
  Algorithm	p. 127
  Experimental Results	p. 130
  Optimizing Circuits for Linear Nearest Neighbor Architectures	p. 131
  NNC-optimal Decomposition	p. 133
  Optimizing NNC-optimal Decomposition	p. 134
  Experimental Results	p. 138
  Summary and Future Work	p. 138
  Formal Verification and Debugging	p. 143
  Equivalence Checking	p. 144
  The Equivalence Checking Problem	p. 145
  QMDD-based Equivalence Checking	p. 145
  SAT-based Equivalence Checking	p. 148
  Experimental Results	p. 150
  Automated Debugging and Fixing	p. 154
  The Debugging Problem	p. 155
  Determining Error Candidates	p. 157
  Determining Error Locations	p. 161
  Fixing Erroneous Circuits	p. 165
  Experimental Results	p. 167
  Summary and Future Work	p. 173
  Summary and Conclusions	p. 175
  References	p. 177
  Index	p. 183
  Table of Contents provided by Ingram. All Rights Reserved.

기본정보

ISBN	9789048195787 ( 9048195780 )
발행(출시)일자	2010년 08월 18일
쪽수	184쪽
크기	156 * 234 * 13 mm / 458 g
총권수	1권
언어	영어