Monolithic Phase-Locked Loops and Clock Recovery Circuits

Paperback

Razavi, Behzad (Edt) 저자(글)

Wiley-IEEE Press · 1996년 04월 18일

책 소개

Featuring an extensive 40 page tutorial introduction, this carefully compiled anthology of 65 of the most important papers on phase-locked loops and clock recovery circuits brings you comprehensive coverage of the field-all in one self-contained volume. You'll gain an understanding of the analysis, design, simulation, and implementation of phase-locked loops and clock recovery circuits in CMOS and bipolar technologies along with valuable insights into the issues and trade-offs associated with phase locked systems for high speed, low power, and low noise.
Preface.Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits-A Tutorial (B. Razavi).BASIC THEORY.Theory of AFC Synchronization (W. Gruen).Color-Carrier Reference Phase Synchronization Accuracy in NTSC Color Television (D. Richman).Charge-Pump Phase-Locked Loops (F. Gardner).z-Domain Model for Discrete-Time PLLs (J. Hein & J. Scott).Analyze PLLs with Discrete Time Modeling (J. Kovacs).Properties of Frequency Difference Detectors (F. Gardner).Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery (D. Messerschmitt).Analysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission (E. Roza).Optimization of Phase-Locked Loop Performance in Data Recovery Systems (R. Co & J. Mulligan).Noise Properties of PLL Systems (V. Kroupa).PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design (B. Kim, et al.).Practical Approach Augurs PLL Noise in RF Synthesizers (M. O'Leary).The Effects of Noise in Oscillators (E. Hafner).A Simple Model of Feedback Oscillator Noise Spectrum (D. Leeson).Noise in Relaxation Oscillators (A. Abidi & R. Meyer).Analysis of Timing Jitter in CMOS Ring Oscillators (T. Weigandt, et al.).Analysis, Modeling, and Simulation of Phase Noise in Monolithic Voltage-Controlled Oscillators (B. Razavi).BUILDING BLOCKS.Start-up and Frequency Stability in High-Frequency Oscillators (N. Nguyen & R. Meyer).MOS Oscillators with Multi-Decade Tuning Range and Gigahertz Maximum Speed (M. Banu).A Bipolar 1 GHz Multi-Decade Monolithic Variable-Frequency Oscillator (J. Wu).A Digital Phase and Frequency Sensitive Detector (J. Brown).A 3-State Phase Detector Can Improve Your Next PLL Design (C. Sharpe).GaAs Monolithic Phase/Frequency Discriminator (I. Shahriary, et al.).A New Phase-Locked Loop Timing Recovery Method for Digital Regenerators (J. Bellisio).A Phase-Locked Loop with Digital Frequency Comparator for Timing Signal Recovery (J. Afonso, et al.).Clock Recovery from Random Binary Signals (J. Alexander).A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s (A. Pottbacker, et al.).A Self-Correcting Clock Recovery Circuit (C. Hogge).MODELING AND SIMULATION.An Integrated PLL Clock Generator for 275 MHz Graphic Displays (G. Gutierrez & D. DeSimone).The Macro Modeling of Phase-Locked Loopes for the SPICE Simulator (M. Sitkowski).Modeling and Simulation of an Analog Charge Pump Phase-Locked Loop (S. Can & Y. Sahinkaya).Mixed-Mode Simulation of Phase-Locked Loops (B. Antao, et al.).Behavioral Representation for VCO and Detectors in Phase-Lock Systems (E. Liu & A. Sangiovanni-Vincentelli).Behavioral Simulation Techniques for Phase/Delay-Locked Systems (A. Demir, et al.).PHASE-LOCKED LOOPS.A Monolithic Phase-Locked Loop with Detection Processor (E. Murthi).A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors (K. Ware, et al.).High-Frequency Phase-Locked Loops in Monolithic Bipolar Technology (M. Soyuer & R. Meyer).A 6-GHz Integrated Phase-Locked Loop Using AlGaAs/GaAs Heterojunction Bipolar Transistors (A. Buchwald, et al.).A 6-GHz 60-mW BiCMOS Phase-Locked Loop with 2-V Supply (B. Razavi & J. Sung).Design of PLL-Based Clock Generation Circuits (D. Jeong).A Variable Delay Line PLL for CPU-Coprocessor Synchronization (M. Johnson & E. Hudson).&

작가정보

저자(글) Razavi, Behzad (Edt)

목차

• Preface
  Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits—A Tutorial
  Basic Theory
  Theory of AFC Synchronization
  Color-Carrier Reference Phase Synchronization Accuracy in NTSC Color Television
  Charge-Pump Phase-Locked Loops
  z-Domain Model for Discrete-Time PLLs
  Analyze PLLs with Discrete Time Modeling
  Properties of Frequency Difference Detectors
  Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery
  Analysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission
  Optimization of Phase-Locked Loop Performance in Data Recovery Systems
  Noise Properties of PLL Systems
  PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design
  Practical Approach Augurs PLL Noise in RF Synthesizers
  The Effects of Noise in Oscillators
  A Simple Model of Feedback Oscillator Noise Spectrum
  Noise in Relaxation Oscillators
  Analysis of Timing Jitter in CMOS Ring Oscillators
  Analysis, Modeling, and Simulation of Phase Noise in Monolithic Voltage-Controlled Oscillators
  Building Blocks
  Start-up and Frequency Stability in High-Frequency Oscillators
  MOS Oscillators with Multi-Decade Tuning Range and Gigahertz Maximum Speed
  A Bipolar 1 GHz Multi-Decade Monolithic Variable-Frequency Oscillator
  A Digital Phase and Frequency Sensitive Detector
  A 3-State Phase Detector Can Improve Your Next PLL Design
  GaAs Monolithic Phase/Frequency Discriminator
  A New Phase-Locked Loop Timing Recovery Method for Digital Regenerators
  A Phase-Locked Loop with Digital Frequency Comparator for Timing Signal Recovery
  Clock Recovery from Random Binary Signals
  A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s
  A Self-Correcting Clock Recovery Circuit
  Modeling and Simulation
  An Integrated PLL Clock Generator for 275 MHz Graphic Displays
  The Macro Modeling of Phase-Locked Loopes for the SPICE Simulator
  Modeling and Simulation of an Analog Charge Pump Phase-Locked Loop
  Mixed-Mode Simulation of Phase-Locked Loops
  Behavioral Representation for VCO and Detectors in Phase-Lock Systems
  Behavioral Simulation Techniques for Phase/Delay-Locked Systems
  PHASE-LOCKED LOOPS.A Monolithic Phase-Locked Loop with Detection Processor
  A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors
  High-Frequency Phase-Locked Loops in Monolithic Bipolar Technology
  A 6-GHz Integrated Phase-Locked Loop Using AlGaAs/GaAs Heterojunction Bipolar Transistors
  A 6-GHz 60-mW BiCMOS Phase-Locked Loop with 2-V Supply
  Design of PLL-Based Clock Generation Circuits
  A Variable Delay Line PLL for CPU-Coprocessor Synchronization
  Table of Contents provided by Publisher. All Rights Reserved.

기본정보

ISBN	9780780311497 ( 0780311493 )
발행(출시)일자	1996년 04월 18일
쪽수	508쪽
크기	205 * 281 * 27 mm / 1170 g
총권수	1권
언어	영어